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author | Matt Roper <matthew.d.roper@intel.com> | 2023-02-01 14:28:28 -0800 |
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committer | Matt Roper <matthew.d.roper@intel.com> | 2023-02-08 09:40:34 -0800 |
commit | 4039e44237e8ebb06f0e4af549fbedf7c41df9db (patch) | |
tree | bb3a2b081f6fa4c448367983b3fe82a508172b8a /tools/perf/scripts/python/export-to-postgresql.py | |
parent | 9310dba467990d393942cfd0c77acf21484050da (diff) |
drm/i915/pvc: Annotate two more workaround/tuning registers as MCR
XEHPC_LNCFMISCCFGREG0 and XEHPC_L3SCRUB are both in MCR register ranges
on PVC (with HALFBSLICE and L3BANK replication respectively), so they
should be explicitly declared as MCR registers and use MCR-aware
workaround handlers.
The workarounds/tuning settings should still be applied properly on PVC
even without the MCR annotation, but readback verification on
CONFIG_DRM_I915_DEBUG_GEM builds could potentitally give false positive
"workaround lost on load" warnings on parts fused such that a unicast
read targets a terminated register instance.
Fixes: a9e69428b1b4 ("drm/i915: Define MCR registers explicitly")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230201222831.608281-1-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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