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authorIlya <Ilya.Bakoulin@amd.com>2022-01-27 14:14:32 -0500
committerAlex Deucher <alexander.deucher@amd.com>2022-02-07 18:03:49 -0500
commit39da460fd4c0f8e7290dcc9cbfc9375de9d0eeca (patch)
tree7e68da2285094e0d5e67c6c774c7599d85ec5d4f /tools/perf/scripts/python/export-to-postgresql.py
parent559e2655220d56f939a9fbc6212992345025392c (diff)
drm/amd/display: Fix DP LT sequence on EQ fail
[Why] The number of lanes wasn't being reset to maximum when reducing link rate due to an EQ failure. This could result in having fewer lanes in the verified link capabilities, a lower maximum link bandwidth, and fewer modes being supported. [How] Reset the number of lanes to max when dropping link rate due to EQ failure during link training. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Ilya <Ilya.Bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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