diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-09-01 16:04:39 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-09-20 22:32:22 +0300 |
| commit | 26f03ef816632945bec135f12a7f902b2de3a0c3 (patch) | |
| tree | 4c83e3e9257b00d19ad2b4e3c63b2e59d6f2a610 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 0ce013a4e840528fcd1c80a264fd47fa5be6a515 (diff) | |
drm/i915: Assert that VRR is off during vblank evasion if necessary
Whenever we change the actual transcoder timings (clock via
seamless M/N, full modeset, (or soon) vtotal via LRR) we
want the timing generator to be in non-VRR during the commit.
Warn if we forgot to turn VRR off prior to vblank evasion.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230901130440.2085-12-ville.syrjala@linux.intel.com
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions