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authorDuy Nguyen <duy.nguyen.rh@renesas.com>2024-02-01 15:19:16 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2024-02-22 11:03:32 +0100
commit20a942d60b34719df8a145e0364e90981380aefb (patch)
tree9ac595edb85f206cd857897bd21cc123df822504 /tools/perf/scripts/python/export-to-postgresql.py
parent93e28f88710b2cbe51d6fe760cdf53fc9621f33c (diff)
arm64: dts: renesas: r8a779h0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be
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