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authorIlpo Järvinen <ilpo.jarvinen@linux.intel.com>2024-12-16 19:56:09 +0200
committerBjorn Helgaas <bhelgaas@google.com>2025-02-18 15:40:52 -0600
commit1f82b7e84a09cac05ec24cd8dbc68d7fe9ba0d97 (patch)
tree3b5b7b12ebb0797a24f173fd70a7a4bdd784f643 /tools/perf/scripts/python/export-to-postgresql.py
parentd06cc1e3809040e8250f69a4c656e3717e6b963c (diff)
PCI: Use min_align, not unrelated add_align, for size0
Commit 566f1dd52816 ("PCI: Relax bridge window tail sizing rules") relaxed bridge window tail alignment rule for the non-optional part (size0, no add_size/add_align). The required alignment given for pbus_upstream_space_available(), however, was add_align which relates only to size1 alignment. As pbus_upstream_space_available() only selects between normal and relaxed tail alignment of the bridge window, the different alignment only makes relaxed tail alignment to be used more often than what was intended, which should be harmless because relaxed tail alignment itself should work in all cases. For consistency, change pbus_upstream_space_available() call to use min_align which is the alignment that is going to be used for the bridge window in the case where size0 sized allocation is attempted. Link: https://lore.kernel.org/r/20241216175632.4175-3-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Xiaochun Lee <lixc17@lenovo.com>
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