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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-02-08 21:11:40 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-02-16 12:29:47 -0800 |
| commit | 0d53879faada6278209883a9eebf39b9e3a8ba10 (patch) | |
| tree | 297b50571116af41c33b2a3957e37d74c5b6404c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | bd3de31950aecc29abc6e554e3b3f6883080c5be (diff) | |
drm/i915/gt: Order GT registers by MMIO offset
The random order of register definitions we have today causes a lot of
confusion and unintentional duplication when new registers/bits are
added to the driver. Let's order the GT register file by MMIO offset
A couple duplicated/unused register definitions are dropped while doing
this re-order: GEN11_GT_INTR_DW{0,1}, GEN11_IIR_REG{0,1}_SELECTOR, and
GEN11_INTR_IDENTITY_REG{0,1} aren't used anywhere in the driver because
we have other parameterized macros referencing those registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220209051140.1599643-7-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions