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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-02-19 17:23:32 +0100 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-02-26 12:15:49 +0200 |
| commit | de36ea80b303da228844cd9379232aa4e3825f58 (patch) | |
| tree | 529c17c54096774220a8efe005236a6f885af241 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | 52b3f0e118b1700e5c60ff676a1f522ce44fadc8 (diff) | |
drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLL
Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent
updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock
Framework. pll_7nm_register() still used in one place previous
readl+writel, which can be simplified with this new wrapper.
This is purely for readability and simplification and should have no
functional impact, because the code touched here is before clock is
registered via CCF, so there is no concurrency issue.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/638323/
Link: https://lore.kernel.org/r/20250219-drm-msm-phy-pll-cfg-reg-v5-1-d28973fa513a@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions