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| author | Arnd Bergmann <arnd@arndb.de> | 2023-08-12 10:44:02 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-08-12 10:44:03 +0200 |
| commit | e5963e159655253cf6f106c6eed4557290696783 (patch) | |
| tree | ed8a04f863675a20c163de31d296749fac260c92 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | bda81ccce5e76f56e744c7323cb4fa00726067bb (diff) | |
| parent | cf0e27cd011775f63001e1e925969106c9464fca (diff) | |
Merge tag 'zynqmp-dt-for-6.6' of https://github.com/Xilinx/linux-xlnx into soc/dt
arm64: ZynqMP DT changes for v6.6
- Describe caches
- Fix i2c gpio recovery description
- Setting up default i2c frequency
- Describe GEM TSU clock and assigned rates for SOMs
- Reserved 1MB for internal firmware usage
- Fix dwc3 IRQ description
- Describe interrupts by using macros
* tag 'zynqmp-dt-for-6.6' of https://github.com/Xilinx/linux-xlnx:
arm64: zynqmp: Describe interrupts by using macros
arm64: zynqmp: Fix dwc3 usb interrupt description
arm64: zynqmp: Add memory reserved node for k26 Kria SOM board
arm64: zynqmp: Assign TSU clock frequency for GEMs
arm64: zynqmp: Setting default i2c clock frequency to 400kHz
arm64: zynqmp: Fix open drain warning on ZynqMP
arm64: zynqmp: Add L2 cache nodes
Link: https://lore.kernel.org/r/fde6d7b4-c751-219d-3ec5-04e5bad2aa17@monstr.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
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