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| author | Zhang Rui <rui.zhang@intel.com> | 2025-06-11 14:50:26 +0800 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2025-08-09 21:24:46 -0400 |
| commit | 3a088b07c4f10bf577f4a2392111704195a794ba (patch) | |
| tree | d804fa2e10444fee7750e2cb27ae32afc600a6a5 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | dcd1c379b0f179763956e8596ad99912165a95ec (diff) | |
tools/power turbostat: Fix DMR support
Together with the RAPL MSRs, there are more MSRs gone on DMR, including
PLR (Perf Limit Reasons), and IRTL (Package cstate Interrupt Response
Time Limit) MSRs. The configurable TDP info should also be retrieved
from TPMI based Intel Speed Select Technology feature.
Remove the access of these MSRs for DMR. Improve the DMR platform
feature table to make it more readable at the same time.
Fixes: 83075bd59de2 ("tools/power turbostat: Add initial support for DMR")
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions