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authorRasmus Villemoes <linux@rasmusvillemoes.dk>2023-06-20 13:38:54 +0200
committerJakub Kicinski <kuba@kernel.org>2023-06-22 19:48:37 -0700
commit5c844d57aa7894154e49cf2fc648bfe2f1aefc1c (patch)
tree83857be9935b39fb3526e2ff6b756307c7054b48 /scripts/generate_rust_target.rs
parentece28ecbec9f63e3f722d7c9a99fb965cbeafc1b (diff)
net: dsa: microchip: fix writes to phy registers >= 0x10
According to the errata sheets for ksz9477 and ksz9567, writes to the PHY registers 0x10-0x1f (i.e. those located at addresses 0xN120 to 0xN13f) must be done as a 32 bit write to the 4-byte aligned address containing the register, hence requires a RMW in order not to change the adjacent PHY register. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Reviewed-by: Simon Horman <simon.horman@corigine.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20230620113855.733526-4-linux@rasmusvillemoes.dk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'scripts/generate_rust_target.rs')
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