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| author | Conor Dooley <conor.dooley@microchip.com> | 2024-05-08 16:46:51 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-05-17 12:15:09 +0200 |
| commit | 4ec012171604507a72e314c46592bcb6db0d317e (patch) | |
| tree | 340f7c9e7be8209945e69fd6694f164f319f02fc /scripts/generate_rust_analyzer.py | |
| parent | ebed91287cb58098c11c309e514a98fe7656aa7d (diff) | |
spi: microchip-core-qspi: fix setting spi bus clock rate
commit ef13561d2b163ac0ae6befa53bca58a26dc3320b upstream.
Before ORing the new clock rate with the control register value read
from the hardware, the existing clock rate needs to be masked off as
otherwise the existing value will interfere with the new one.
CC: stable@vger.kernel.org
Fixes: 8596124c4c1b ("spi: microchip-core-qspi: Add support for microchip fpga qspi controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240508-fox-unpiloted-b97e1535627b@spud
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions