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| author | Anand Moon <linux.amoon@gmail.com> | 2025-08-25 12:21:42 +0530 |
|---|---|---|
| committer | Neil Armstrong <neil.armstrong@linaro.org> | 2025-09-04 15:10:15 +0200 |
| commit | fd7b48b1f91e1830e22e73744e7525af24d8ae25 (patch) | |
| tree | c019633ad7ed597e9715acf14e40f814cdeb2847 /rust/kernel | |
| parent | d7fc05da8ba28d22fb9bd79d9308f928fcb81c19 (diff) | |
arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
As per S905X3 datasheet add missing cache information to the Amlogic
SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.
- Each Cortex-A55 core has 32KB of L1 instruction cache available and
32KB of L1 data cache available.
- Along with 256KB Unified L2 cache.
Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-3-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Diffstat (limited to 'rust/kernel')
0 files changed, 0 insertions, 0 deletions