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authorSvyatoslav Ryhel <clamor95@gmail.com>2025-08-29 15:22:32 +0300
committerThierry Reding <treding@nvidia.com>2025-09-11 18:29:48 +0200
commit8e7bd526e83673c2b4931163311cca49796657f8 (patch)
treea0b013e74b3e8533bbb06d7739935bad777e4889 /rust/kernel
parentc4d7901225435c2a82049588532f7b7a07e06188 (diff)
clk: tegra: Add DFLL DVCO reset control for Tegra114
The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124") Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'rust/kernel')
0 files changed, 0 insertions, 0 deletions