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| author | Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> | 2025-09-04 14:52:23 +0800 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-09-04 22:24:04 +0530 |
| commit | 37bf0f4e39de9b53bc6f8d3702b021e2c6b5bae3 (patch) | |
| tree | 671eeb164f843a9b90e0a273f993b84159257b92 /rust/kernel/alloc/kvec/errors.rs | |
| parent | 45df22935bdc6bbddf87f38a57ae7257244cf3cf (diff) | |
PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
Add lane equalization setting for 8.0 GT/s and 32.0 GT/s to enhance link
stability and avoid AER Correctable Errors reported on some platforms
(eg. SA8775P).
8.0 GT/s, 16.0 GT/s and 32.0 GT/s require the same equalization setting.
This setting is programmed into a group of shadow registers, which can be
switched to configure equalization for different speeds by writing 00b,
01b and 10b to `RATE_SHADOW_SEL`.
Hence, program equalization registers in a loop using link speed as index,
so that equalization setting can be programmed for 8.0 GT/s, 16.0 GT/s
and 32.0 GT/s.
Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes")
Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
[mani: wrapped the warning to fit 100 columns, used post-increment for loop]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250904065225.1762793-2-ziyue.zhang@oss.qualcomm.com
Diffstat (limited to 'rust/kernel/alloc/kvec/errors.rs')
0 files changed, 0 insertions, 0 deletions