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author | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:20 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-10-03 12:13:20 -0500 |
commit | 531abff0fa53bc3a2f7f69b2693386eb6bda96e5 (patch) | |
tree | e02204d3458dd50e359e85828d8d5bc62c072bd4 /rust/helpers | |
parent | 93f32da3d409a29187e0bbc940a9ed619c754cce (diff) | |
parent | 0da48c5b2fa731b21bc523c82d927399a1e508b0 (diff) |
Merge branch 'pci/controller/qcom'
- Select PCI Power Control Slot driver so slot voltage rails can be turned
on/off if described in Root Port device tree node (Qiang Yu)
- Parse only PCI bridge child nodes in device tree, skipping unrelated
nodes such as OPP (Operating Performance Points), which caused probe
failures (Krishna Chaitanya Chundru)
- Add 8.0 GT/s and 32.0 GT/s equalization settings (Ziyue Zhang)
- Fix typo in CURSOR macro names (Ziyue Zhang)
- Consolidate Root Port 'phy' and 'reset' properties in struct
qcom_pcie_port, regardless of whether we got them from the Root Port node
or the host bridge node (Manivannan Sadhasivam)
- Fetch and map the ELBI register space in the DWC core rather than in each
driver individually (Krishna Chaitanya Chundru)
- Enable ECAM mechanism in DWC core by setting up iATU with 'CFG Shift
Feature' and use this in the qcom driver (Krishna Chaitanya Chundru)
* pci/controller/qcom:
PCI: dwc: Support ECAM mechanism by enabling iATU 'CFG Shift Feature'
PCI: qcom: Prepare for the DWC ECAM enablement
PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'
PCI: dwc: Add support for ELBI resource mapping
PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port
PCI: qcom: Fix macro typo for CURSOR
PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
PCI: qcom: Restrict port parsing only to PCIe bridge child nodes
PCI: qcom: Select PCI Power Control Slot driver
Diffstat (limited to 'rust/helpers')
0 files changed, 0 insertions, 0 deletions