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| author | Anand Moon <linux.amoon@gmail.com> | 2025-08-25 12:21:51 +0530 |
|---|---|---|
| committer | Neil Armstrong <neil.armstrong@linaro.org> | 2025-09-04 15:10:15 +0200 |
| commit | e97fdb9b8a0f8bd349de48815694f8a7200e3d62 (patch) | |
| tree | db215c9f2898f8a869faafb5d82c8a656d6736b9 /rust/helpers/security.c | |
| parent | e7f85e6c155aed3e10e698dd05bd04b2d52edb59 (diff) | |
arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
As per T7 datasheet add missing cache information to the Amlogic T7 SoC.
- Each Cortex-A53 core has 32 KB of instruction cache and
32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
64 KB of L1 data cache available.
- The little (A53) cluster has 256 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.
Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-12-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Diffstat (limited to 'rust/helpers/security.c')
0 files changed, 0 insertions, 0 deletions