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| author | Anand Moon <linux.amoon@gmail.com> | 2025-08-25 12:21:44 +0530 |
|---|---|---|
| committer | Neil Armstrong <neil.armstrong@linaro.org> | 2025-09-04 15:10:15 +0200 |
| commit | 3b6ad2a433672f4ed9e1c90e4ae6b94683d1f1a2 (patch) | |
| tree | 4de5a24eb1e7f53eef05ecd3e0111551ec3f5f70 /rust/helpers/security.c | |
| parent | a4428e52babdb682f47f99b0b816e227e51a3835 (diff) | |
arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
As per the AXG datasheet add missing cache information to the Amlogic AXG
SoC.
- Each Cortex-A53 core has 32KB of L1 instruction cache available and
32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.
Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-5-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Diffstat (limited to 'rust/helpers/security.c')
0 files changed, 0 insertions, 0 deletions