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author | Saaem Rizvi <SyedSaaem.Rizvi@amd.com> | 2023-03-06 15:10:13 -0500 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-08-23 17:52:41 +0200 |
commit | 4bdfe20d85b32274234bbcd705d5547fd70a4ea1 (patch) | |
tree | d33c65839ff90423a7d67ef0dfb67709bd45072a /net/unix/af_unix.c | |
parent | 8517d739923e054d774d6004e1c60e9793588502 (diff) |
drm/amd/display: Implement workaround for writing to OTG_PIXEL_RATE_DIV register
commit 74fa4c81aadf418341f0d073c864ea7dca730a2e upstream.
[Why and How]
Current implementation requires FPGA builds to take a different
code path from DCN32 to write to OTG_PIXEL_RATE_DIV. Now that
we have a workaround to write to OTG_PIXEL_RATE_DIV register without
blanking display on hotplug on DCN32, we can allow the code paths for
FPGA to be exactly the same allowing for more consistent
testing.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "Limonciello, Mario" <mario.limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'net/unix/af_unix.c')
0 files changed, 0 insertions, 0 deletions