diff options
| author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2024-02-16 23:44:57 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-03-01 13:41:55 +0100 |
| commit | 676b3387b08d35dde9d9e861a821c4e1223ef62c (patch) | |
| tree | cbb5ae54c34fdca44b6eb070c382f184304efe48 /kernel/bpf/helpers.c | |
| parent | 8444555cb53ad61eb2a3b2b58a4dba630d4ed9c2 (diff) | |
ata: ahci_ceva: fix error handling for Xilinx GT PHY support
[ Upstream commit 26c8404e162b43dddcb037ba2d0cb58c0ed60aab ]
Platform clock and phy error resources are not cleaned up in Xilinx GT PHY
error path.
To fix introduce the function ceva_ahci_platform_enable_resources() which
is a customized version of ahci_platform_enable_resources() and inline with
SATA IP programming sequence it does:
- Assert SATA reset
- Program PS GTR phy
- Bring SATA by de-asserting the reset
- Wait for GT lane PLL to be locked
ceva_ahci_platform_enable_resources() is also used in the resume path
as the same SATA programming sequence (as in probe) should be followed.
Also cleanup the mixed usage of ahci_platform_enable_resources() and custom
implementation in the probe function as both are not required.
Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy")
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'kernel/bpf/helpers.c')
0 files changed, 0 insertions, 0 deletions