diff options
| author | Ilya Bakoulin <Ilya.Bakoulin@amd.com> | 2022-07-26 16:19:38 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-09-05 10:27:47 +0200 |
| commit | 5c5cd52ab09d408839f55ccf6fae4a3a58fd0bb7 (patch) | |
| tree | d72b0d7fd1ca3e333bb748d489cc770922c7e60c /fs/btrfs/tree-checker.c | |
| parent | c570198c3d9e406c3312d115d8f87b8fc86b19c3 (diff) | |
drm/amd/display: Fix pixel clock programming
[ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ]
[Why]
Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned
between different HDMI lanes when using YCbCr420 10-bit pixel format.
BIOS functions for transmitter/encoder control take pixel clock in kHz
increments, whereas the function for setting the pixel clock is in 100Hz
increments. Setting pixel clock to a value that is not on a kHz boundary
will cause the issue.
[How]
Round pixel clock down to nearest kHz in 10/12-bpc cases.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'fs/btrfs/tree-checker.c')
0 files changed, 0 insertions, 0 deletions