Merge branch 'pci/capability-search'

- Simplify __pci_find_next_cap_ttl() by replacing magic numbers with
  #defines, extracting fields with FIELD_GET(), etc (Hans Zhang)

- Convert __pci_find_next_cap_ttl() to a PCI_FIND_NEXT_CAP() macro that
  takes a config space accessor function so we can also use it in cases
  where the usual config accessors aren't available (Hans Zhang)

- Similarly convert pci_find_next_ext_capability() to a
  PCI_FIND_NEXT_EXT_CAP() macro (Hans Zhang)

- Implement dwc, dwc endpoint, and cadence capability search interfaces on
  top of PCI_FIND_NEXT_CAP() and PCI_FIND_NEXT_EXT_CAP(), replacing the
  previous duplicated code (Hans Zhang)

- Search for capabilities in the cadence core instead of hard-coding their
  offsets, which are subject to change (Hans Zhang)

* pci/capability-search:
  PCI: cadence: Use cdns_pcie_find_*capability() to avoid hardcoding offsets
  PCI: cadence: Implement capability search using PCI core APIs
  PCI: dwc: ep: Implement capability search using PCI core APIs
  PCI: dwc: Implement capability search using PCI core APIs
  PCI: Refactor extended capability search into PCI_FIND_NEXT_EXT_CAP()
  PCI: Refactor capability search into PCI_FIND_NEXT_CAP()
  PCI: Clean up __pci_find_next_cap_ttl() readability

1 files changed, 42 insertions, 0 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00f52d472dcd..a44f2113925d 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -609,6 +609,27 @@ static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
 	dw_pcie_write_dbi2(pci, reg, 0x4, val);
 }
 
+static inline int dw_pcie_read_cfg_byte(struct dw_pcie *pci, int where,
+					u8 *val)
+{
+	*val = dw_pcie_readb_dbi(pci, where);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static inline int dw_pcie_read_cfg_word(struct dw_pcie *pci, int where,
+					u16 *val)
+{
+	*val = dw_pcie_readw_dbi(pci, where);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static inline int dw_pcie_read_cfg_dword(struct dw_pcie *pci, int where,
+					 u32 *val)
+{
+	*val = dw_pcie_readl_dbi(pci, where);
+	return PCIBIOS_SUCCESSFUL;
+}
+
 static inline unsigned int dw_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,
 						     u8 func_no)
 {
@@ -674,6 +695,27 @@ static inline u8 dw_pcie_ep_readb_dbi(struct dw_pcie_ep *ep, u8 func_no,
 	return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x1);
 }
 
+static inline int dw_pcie_ep_read_cfg_byte(struct dw_pcie_ep *ep, u8 func_no,
+					   int where, u8 *val)
+{
+	*val = dw_pcie_ep_readb_dbi(ep, func_no, where);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static inline int dw_pcie_ep_read_cfg_word(struct dw_pcie_ep *ep, u8 func_no,
+					   int where, u16 *val)
+{
+	*val = dw_pcie_ep_readw_dbi(ep, func_no, where);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static inline int dw_pcie_ep_read_cfg_dword(struct dw_pcie_ep *ep, u8 func_no,
+					    int where, u32 *val)
+{
+	*val = dw_pcie_ep_readl_dbi(ep, func_no, where);
+	return PCIBIOS_SUCCESSFUL;
+}
+
 static inline unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
 						      u8 func_no)
 {