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authorKishon Vijay Abraham I <kishon@ti.com>2018-10-17 13:11:10 +0530
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-10-17 09:59:00 +0100
commit23fe5bd4be90099e760fe0d00665ab1e465255b3 (patch)
treedad2c94df471bd40851fc5351e5b737fc6bb38a0 /drivers/pci/controller/dwc/pcie-designware.h
parentf9127db9fbadd079c6b88974001cb036057c8afc (diff)
PCI: keystone: Cleanup ks_pcie_link_up()
ks_pcie_link_up() uses registers from the designware core to get the status of the link. Move the register defines to pcie-designware.h and cleanup ks_pcie_link_up(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 96126fd8403cc..a4d939536faf4 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -37,6 +37,10 @@
#define PORT_LINK_MODE_4_LANES (0x7 << 16)
#define PORT_LINK_MODE_8_LANES (0xf << 16)
+#define PCIE_PORT_DEBUG0 0x728
+#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
+#define PORT_LOGIC_LTSSM_STATE_L0 0x11
+
#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)