diff options
| author | Takashi Iwai <tiwai@suse.de> | 2011-08-08 14:30:29 +0200 | 
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2011-08-08 14:30:29 +0200 | 
| commit | 0a2d31b62dba9b5b92a38c67c9cc42630513662a (patch) | |
| tree | f755d74ec85248de645e10c45ed1a2ed467530f6 /drivers/net/wireless/ath/ath5k/pcu.c | |
| parent | 8039290a91c5dc4414093c086987a5d7738fe2fd (diff) | |
| parent | df944f66784e6d4f2f50739263a4947885d8b6ae (diff) | |
Merge branch 'fix/kconfig' into for-linus
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/pcu.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath5k/pcu.c | 40 | 
1 files changed, 19 insertions, 21 deletions
| diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c index 712a9ac4000e..067313845060 100644 --- a/drivers/net/wireless/ath/ath5k/pcu.c +++ b/drivers/net/wireless/ath/ath5k/pcu.c @@ -32,7 +32,7 @@  #include "base.h"  /* - * AR5212+ can use higher rates for ack transmition + * AR5212+ can use higher rates for ack transmission   * based on current tx rate instead of the base rate.   * It does this to better utilize channel usage.   * This is a mapping between G rates (that cover both @@ -77,14 +77,13 @@ static const unsigned int ack_rates_high[] =  int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,  		int len, struct ieee80211_rate *rate, bool shortpre)  { -	struct ath5k_softc *sc = ah->ah_sc;  	int sifs, preamble, plcp_bits, sym_time;  	int bitrate, bits, symbols, symbol_bits;  	int dur;  	/* Fallback */  	if (!ah->ah_bwmode) { -		__le16 raw_dur = ieee80211_generic_frame_duration(sc->hw, +		__le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,  					NULL, len, rate);  		/* subtract difference between long and short preamble */ @@ -205,7 +204,7 @@ unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)   */  void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)  { -	struct ath5k_statistics *stats = &ah->ah_sc->stats; +	struct ath5k_statistics *stats = &ah->stats;  	/* Read-And-Clear */  	stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); @@ -240,25 +239,24 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)   */  static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)  { -	struct ath5k_softc *sc = ah->ah_sc;  	struct ieee80211_rate *rate;  	unsigned int i;  	/* 802.11g covers both OFDM and CCK */  	u8 band = IEEE80211_BAND_2GHZ;  	/* Write rate duration table */ -	for (i = 0; i < sc->sbands[band].n_bitrates; i++) { +	for (i = 0; i < ah->sbands[band].n_bitrates; i++) {  		u32 reg;  		u16 tx_time;  		if (ah->ah_ack_bitrate_high) -			rate = &sc->sbands[band].bitrates[ack_rates_high[i]]; +			rate = &ah->sbands[band].bitrates[ack_rates_high[i]];  		/* CCK -> 1Mb */  		else if (i < 4) -			rate = &sc->sbands[band].bitrates[0]; +			rate = &ah->sbands[band].bitrates[0];  		/* OFDM -> 6Mb */  		else -			rate = &sc->sbands[band].bitrates[4]; +			rate = &ah->sbands[band].bitrates[4];  		/* Set ACK timeout */  		reg = AR5K_RATE_DUR(rate->hw_value); @@ -534,9 +532,9 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)  	local_irq_restore(flags); -	WARN_ON( i == ATH5K_MAX_TSF_READ ); +	WARN_ON(i == ATH5K_MAX_TSF_READ); -	return (((u64)tsf_upper1 << 32) | tsf_lower); +	return ((u64)tsf_upper1 << 32) | tsf_lower;  }  /** @@ -586,7 +584,7 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)  	/*  	 * Set the additional timers by mode  	 */ -	switch (ah->ah_sc->opmode) { +	switch (ah->opmode) {  	case NL80211_IFTYPE_MONITOR:  	case NL80211_IFTYPE_STATION:  		/* In STA mode timer1 is used as next wakeup @@ -623,8 +621,8 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)  	 * Set the beacon register and enable all timers.  	 */  	/* When in AP or Mesh Point mode zero timer0 to start TSF */ -	if (ah->ah_sc->opmode == NL80211_IFTYPE_AP || -	    ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT) +	if (ah->opmode == NL80211_IFTYPE_AP || +	    ah->opmode == NL80211_IFTYPE_MESH_POINT)  		ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);  	ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); @@ -643,14 +641,14 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)  	/* Flush any pending BMISS interrupts on ISR by  	 * performing a clear-on-write operation on PISR  	 * register for the BMISS bit (writing a bit on -	 * ISR togles a reset for that bit and leaves -	 * the rest bits intact) */ +	 * ISR toggles a reset for that bit and leaves +	 * the remaining bits intact) */  	if (ah->ah_version == AR5K_AR5210)  		ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);  	else  		ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); -	/* TODO: Set enchanced sleep registers on AR5212 +	/* TODO: Set enhanced sleep registers on AR5212  	 * based on vif->bss_conf params, until then  	 * disable power save reporting.*/  	AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); @@ -738,7 +736,7 @@ ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)  	dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;  	/* NOTE: SWBA is different. Having a wrong window there does not -	 * stop us from sending data and this condition is catched thru +	 * stop us from sending data and this condition is caught by  	 * other means (SWBA interrupt) */  	if (ath5k_check_timer_win(nbtt, atim, 1, intval) && @@ -814,7 +812,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)  	struct ath_common *common = ath5k_hw_common(ah);  	u32 pcu_reg, beacon_reg, low_id, high_id; -	ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); +	ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);  	/* Preserve rest settings */  	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; @@ -890,13 +888,13 @@ void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,  	 * XXX: rethink this after new mode changes to  	 * mac80211 are integrated */  	if (ah->ah_version == AR5K_AR5212 && -		ah->ah_sc->nvifs) +		ah->nvifs)  		ath5k_hw_write_rate_duration(ah);  	/* Set RSSI/BRSSI thresholds  	 *  	 * Note: If we decide to set this value -	 * dynamicaly, have in mind that when AR5K_RSSI_THR +	 * dynamically, have in mind that when AR5K_RSSI_THR  	 * register is read it might return 0x40 if we haven't  	 * wrote anything to it plus BMISS RSSI threshold is zeroed.  	 * So doing a save/restore procedure here isn't the right | 
