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author | Emil Tantilov <emil.s.tantilov@intel.com> | 2024-11-21 20:40:59 -0800 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-02-08 09:58:03 +0100 |
commit | 7f42a905db2ef8bc0ff039aa492d92db0e5f09ea (patch) | |
tree | b6dd58d6bdeff6e5b366d073693f843124ec8245 /drivers/net/ethernet/intel/ice/ice_parser_rt.c | |
parent | e468aace407447c1c506b230fd30be36c4e9479f (diff) |
idpf: add read memory barrier when checking descriptor done bit
[ Upstream commit 396f0165672c6a74d7379027d344b83b5f05948c ]
Add read memory barrier to ensure the order of operations when accessing
control queue descriptors. Specifically, we want to avoid cases where loads
can be reordered:
1. Load #1 is dispatched to read descriptor flags.
2. Load #2 is dispatched to read some other field from the descriptor.
3. Load #2 completes, accessing memory/cache at a point in time when the DD
flag is zero.
4. NIC DMA overwrites the descriptor, now the DD flag is one.
5. Any fields loaded before step 4 are now inconsistent with the actual
descriptor state.
Add read memory barrier between steps 1 and 2, so that load #2 is not
executed until load #1 has completed.
Fixes: 8077c727561a ("idpf: add controlq init and reset checks")
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Sridhar Samudrala <sridhar.samudrala@intel.com>
Suggested-by: Lance Richardson <rlance@google.com>
Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Krishneil Singh <krishneil.k.singh@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_parser_rt.c')
0 files changed, 0 insertions, 0 deletions