diff options
| author | Arun Ramadoss <arun.ramadoss@microchip.com> | 2022-07-01 20:41:24 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-07-02 16:34:05 +0100 |
| commit | f597d3ad75b85083f6f129a7ee25da2b67efefce (patch) | |
| tree | 798d0d5ece5f38bd110e25c6b78e68965c9d6aaf /drivers/net/dsa/microchip/lan937x_reg.h | |
| parent | c14e878d4a4f6f5e1f58e83ac25363a1b80fa374 (diff) | |
net: dsa: microchip: lan937x: add phylink_mac_link_up support
This patch add support for phylink_mac_link_up. It configures the mac
for the speed, flow control and duplex mode.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/microchip/lan937x_reg.h')
| -rw-r--r-- | drivers/net/dsa/microchip/lan937x_reg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 19f3aa3442289..c187d0a3e7fa0 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -139,6 +139,17 @@ #define PORT_MII_RX_FLOW_CTRL BIT(3) #define PORT_GRXC_ENABLE BIT(0) +#define REG_PORT_XMII_CTRL_1 0x0301 +#define PORT_MII_NOT_1GBIT BIT(6) +#define PORT_MII_SEL_EDGE BIT(5) +#define PORT_RGMII_ID_IG_ENABLE BIT(4) +#define PORT_RGMII_ID_EG_ENABLE BIT(3) +#define PORT_MII_MAC_MODE BIT(2) +#define PORT_MII_SEL_M 0x3 +#define PORT_RGMII_SEL 0x0 +#define PORT_RMII_SEL 0x1 +#define PORT_MII_SEL 0x2 + /* 4 - MAC */ #define REG_PORT_MAC_CTRL_0 0x0400 #define PORT_CHECK_LENGTH BIT(2) |