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| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-12-02 10:23:54 +0200 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-12-02 16:42:00 +0200 |
| commit | 89b3c3c7ee9d9be319b90af3d52f00feba04f1d8 (patch) | |
| tree | a64286b8de69cfe36c679fbc6268c57fc09fd0a8 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | f7044dd904d7a97967af097515da272fa89b00e9 (diff) | |
drm/i915/glk: Reuse broxton's cdclk code for GLK
Geminilake has the same register layout, reference clock and programming
sequence as broxton. The difference is that it doesn't support the 1.5
divider and has different ratios, but a lot of code can be shared
between the two platforms.
v2: Rebase (s/broxton/bxt).
v3: Fix vco calculation in glk_de_pll_vco().
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-7-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
0 files changed, 0 insertions, 0 deletions