diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2024-10-10 15:43:04 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-10-11 14:37:40 -0700 |
| commit | 171596bfc36cd2c657a7c17f33a522b75d940a0a (patch) | |
| tree | 0f613f6dec10cc84fb5e2e0945af3223848b337f /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | a6e40f6d757d5e8b0ac621b1a1cfdf3dc3bac6e9 (diff) | |
drm/i915/xe3lpd: Add new display power wells
Xe3's power well handling is similar to previous platforms, but there
are a few changes that need to be handled to ensure optimal power
management:
- PGB now only depends on PG1, not PG2
- Transcoder B is now in PG1 (was previously in PGB)
- Transcoders C & D are now in PG2 (were previously in PGC/PGD)
- DC states now require PG2 to be off (whereas on Xe2 it could remain
on as a dependency of PGB, although the features inside of it could
not be used).
Bspec: 72519, 68851
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241010224311.50133-4-matthew.s.atwood@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions