diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-20 20:14:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-22 15:45:34 +0300 |
| commit | 199bc8c175d712be1610dcad7f7240ad5c864281 (patch) | |
| tree | 9a824a7a03c8666ff6f5cece2c96c309cfc0a7a9 /drivers/gpu/drm/i915/display/intel_cursor_regs.h | |
| parent | 9cad70a9401f4d962e1baa9d607a291bfdc8f010 (diff) | |
drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
s/mtl+/tgl+/ as that's where this was introduced
Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
actually match the normal CUR_CTL register
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240520171459.9661-1-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cursor_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 270c26c2e6dff..e58930ff32eae 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -95,4 +95,9 @@ #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) +/* tgl+ */ +#define _SEL_FETCH_CUR_CTL_A 0x70880 +#define _SEL_FETCH_CUR_CTL_B 0x71880 +#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B) + #endif /* __INTEL_CURSOR_REGS_H__ */ |