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authorDaniel Vetter <daniel.vetter@ffwll.ch>2023-04-03 10:25:44 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2023-04-03 10:25:45 +0200
commit1138398d71e8e583669fcec96784471332e488d4 (patch)
treecc832e08796450735ef16b8b75298cd9bb011a88 /drivers/gpu/drm/amd/display/dc/link/link_validation.c
parent63758fec651f2fe7eab0c5a833f84795911c36e9 (diff)
parentfeae1bd80ec69a3a0011ba1fb88994785f705e3e (diff)
Merge tag 'amd-drm-next-6.4-2023-03-31' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.4-2023-03-31: amdgpu: - Misc code cleanups - S4 fixes - MES fixes - SR-IOV fixes - Link DC backlight to connector device rather than PCI device - W=1 fixes - ASPM quirk - RAS fixes - DC dynamic split fixes and enablement for remaining chips - Navi1x SMU fix - Initial NBIO 7.9 support - Initial GC 9.4.3 support - Initial GFXHUB 1.2 support - Initial MMHUB 1.8 support - DCN 3.1.5 fixes - Initial DC FAMs infrastructure - Add support for 6.75Gbps link rates - Add sysfs nodes for secondary VCN clocks amdkfd: - Initial support for GC 9.4.3 radeon: - Convert to client-based fbdev emulation Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230331221955.7896-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/link/link_validation.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/link/link_validation.c69
1 files changed, 18 insertions, 51 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index 9a5010f86003..d4b7da526f0a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -30,6 +30,7 @@
*/
#include "link_validation.h"
#include "protocols/link_dp_capability.h"
+#include "protocols/link_dp_dpia_bw.h"
#include "resource.h"
#define DC_LOGGER_INIT(logger)
@@ -255,57 +256,6 @@ uint32_t dp_link_bandwidth_kbps(
return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000;
}
-uint32_t link_timing_bandwidth_kbps(const struct dc_crtc_timing *timing)
-{
- uint32_t bits_per_channel = 0;
- uint32_t kbps;
-
- if (timing->flags.DSC)
- return dc_dsc_stream_bandwidth_in_kbps(timing,
- timing->dsc_cfg.bits_per_pixel,
- timing->dsc_cfg.num_slices_h,
- timing->dsc_cfg.is_dp);
-
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- ASSERT(bits_per_channel != 0);
- bits_per_channel = 8;
- break;
- }
-
- kbps = timing->pix_clk_100hz / 10;
- kbps *= bits_per_channel;
-
- if (timing->flags.Y_ONLY != 1) {
- /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
- kbps *= 3;
- if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
- kbps /= 2;
- else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
- kbps = kbps * 2 / 3;
- }
-
- return kbps;
-}
-
static bool dp_validate_mode_timing(
struct dc_link *link,
const struct dc_crtc_timing *timing)
@@ -394,3 +344,20 @@ enum dc_status link_validate_mode_timing(
return DC_OK;
}
+
+bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams)
+{
+ bool ret = true;
+ int bw_needed[MAX_DPIA_NUM];
+ struct dc_link *link[MAX_DPIA_NUM];
+
+ if (!num_streams || num_streams > MAX_DPIA_NUM)
+ return ret;
+
+ for (uint8_t i = 0; i < num_streams; ++i) {
+
+ link[i] = stream[i].link;
+ bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing);
+ }
+ return ret;
+}