diff options
| author | Jun Lei <Jun.Lei@amd.com> | 2022-02-20 13:58:51 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:45:01 -0400 |
| commit | 49f594995a9255ff734f79c1fc22bd06119ebe8f (patch) | |
| tree | 46c7513a070155f507999902ad5bec6d8e5f23ab /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | 452e9214431f1f6385bb20fdf6e1b5692947071f (diff) | |
drm/amd/display: add new pixel rate programming
[why]
New dividers in DCCG need to be programmed depending
on encoder/stream type since pixels per clock in
OTG/DIO is different
DIO also needs additional programming depending on
pixels per clock
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index dd9bb86da4de1..f8d22ba6a6e40 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -576,6 +576,7 @@ struct dcn10_stream_enc_registers { type DP_SEC_GSP11_LINE_NUM #define SE_REG_FIELD_LIST_DCN3_2(type) \ + type DIG_FIFO_OUTPUT_PIXEL_MODE;\ type DIG_SYMCLK_FE_ON;\ type DIG_FIFO_READ_START_LEVEL;\ type DIG_FIFO_ENABLE;\ |