diff options
| author | Charlene Liu <Charlene.Liu@amd.com> | 2020-09-21 14:24:09 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-05 15:16:50 -0400 |
| commit | b15cde19c32d8d543eae2e3cc7c51ba688b12551 (patch) | |
| tree | b3b16876d1ef7894246fb7d87506671a2a1eb58e /drivers/gpu/drm/amd/display/dc/dce80 | |
| parent | 54e8094a76bc8cd41d1ec5c2c2a8755e64349142 (diff) | |
drm/amd/display: Add i2c speed arbitration for dc_i2c and hdcp_i2c
[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.
[how]
Slow down the HW i2c speed when used by HW i2c.
This request: each acquired_i2c_engine setup the i2c speed needed
and sets the I2c engine for HDCP use at release_engine.
This covers SW using HW i2c engine and HDCP using HW i2c engine.
for dmcu using HW i2c engine, needs add similar logic in dmcu fw.
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce80')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index a19be9de2df7d..0eae8cd35f9a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -970,6 +970,7 @@ static bool dce80_construct( pool->base.timing_generator_count = res_cap.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; + dc->caps.i2c_speed_in_khz_hdcp = 40; dc->caps.max_cursor_size = 128; dc->caps.dual_link_dvi = true; dc->caps.extended_aux_timeout_support = false; @@ -1168,6 +1169,7 @@ static bool dce81_construct( pool->base.timing_generator_count = res_cap_81.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; + dc->caps.i2c_speed_in_khz_hdcp = 40; dc->caps.max_cursor_size = 128; dc->caps.is_apu = true; @@ -1365,6 +1367,7 @@ static bool dce83_construct( pool->base.timing_generator_count = res_cap_83.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; + dc->caps.i2c_speed_in_khz_hdcp = 40; dc->caps.max_cursor_size = 128; dc->caps.is_apu = true; |