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authorDave Airlie <airlied@redhat.com>2023-04-17 10:54:58 +1000
committerDave Airlie <airlied@redhat.com>2023-04-17 10:54:59 +1000
commite82c98f2ca439356d5595ba8c9cd782f993f6f8c (patch)
treee07718a52c12f78e247c83f2d6ba14a0058fd819 /drivers/gpu/drm/amd/display/dc/dc.h
parentafa351a15d80993f8ba6ae28652cc23127237e37 (diff)
parent541372bb62f289f4402cf55be51fb9cec7373627 (diff)
Merge tag 'amd-drm-next-6.4-2023-04-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.4-2023-04-14: amdgpu: - S4 fixes for APUs - GFX11 fixes - Misc code cleanups - DCN 3.2 fixes - DCN 3.1.4 fixes - FPO/FAMS work to improve display power savings - DP fixes - UMC 8.10 code cleanup - SDMA v4 fix - GPU clock counter fixes - SMU 13 fixes - Sdma v6 invalidation fix for preemption - RAS fixes - S0ix fix - GC 9.4.3 updates amdkfd: - Fix user pointers with IOMMU - Fix coherency flag handling Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230414204609.7942-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e363a3c88250..23ee63b98dcd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.229"
+#define DC_VER "3.2.230"
#define MAX_SURFACES 3
#define MAX_PLANES 6
@@ -405,6 +405,7 @@ struct dc_config {
bool force_bios_enable_lttpr;
uint8_t force_bios_fixed_vs;
int sdpif_request_limit_words_per_umc;
+ bool use_old_fixed_vs_sequence;
bool disable_subvp_drr;
};
@@ -875,6 +876,9 @@ struct dc_debug_options {
bool override_dispclk_programming;
bool disable_fpo_optimizations;
bool support_eDP1_5;
+ uint32_t fpo_vactive_margin_us;
+ bool disable_fpo_vactive;
+ bool disable_boot_optimizations;
};
struct gpu_info_soc_bounding_box_v1_0;