Merge tag 'drm-next-2025-06-06' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "This is pretty much two weeks worth of fixes, plus one thing that
  might be considered next: amdkfd is now able to be enabled on risc-v
  platforms.

  Otherwise, amdgpu and xe with the majority of fixes, and then a
  smattering all over.

  panel:
   - nt37801: fix IS_ERR
   - nt37801: fix KConfig

  connector:
   - Fix null deref in HDMI audio helper.

  bridge:
   - analogix_dp: fixup clk-disable removal

  nouveau:
   - minor typo fix (',' vs ';')

  msm:
   - mailmap updates

  i915:
   - Fix the enabling/disabling of DP audio SDP splitting
   - Fix PSR register definitions for ALPM
   - Fix u32 overflow in SNPS PHY HDMI PLL setup
   - Fix GuC pending message underflow when submit fails
   - Fix GuC wakeref underflow race during reset

  xe:
   - Two documentation fixes
   - A couple of vm init fixes
   - Hwmon fixes
   - Drop reduntant conversion to bool
   - Fix CONFIG_INTEL_VSEC dependency
   - Rework eviction rejection of bound external bos
   - Stop re-submitting signalled jobs
   - A couple of pxp fixes
   - Add back a fix that got lost in a merge
   - Create LRC bo without VM
   - Fix for the above fix

  amdgpu:
   - UserQ fixes
   - SMU 13.x fixes
   - VCN fixes
   - JPEG fixes
   - Misc cleanups
   - runtime pm fix
   - DCN 4.0.1 fixes
   - Misc display fixes
   - ISP fix
   - VRAM manager fix
   - RAS fixes
   - IP discovery fix
   - Cleaner shader fix for GC 10.1.x
   - OD fix
   - Non-OLED panel fix
   - Misc display fixes
   - Brightness fixes

  amdkfd:
   - Enable CONFIG_HSA_AMD on RISCV
   - SVM fix
   - Misc cleanups
   - Ref leak fix
   - WPTR BO fix

  radeon:
   - Misc cleanups"

* tag 'drm-next-2025-06-06' of https://gitlab.freedesktop.org/drm/kernel: (105 commits)
  drm/nouveau/vfn/r535: Convert comma to semicolon
  drm/xe: remove unmatched xe_vm_unlock() from __xe_exec_queue_init()
  drm/xe: Create LRC BO without VM
  drm/xe/guc_submit: add back fix
  drm/xe/pxp: Clarify PXP queue creation behavior if PXP is not ready
  drm/xe/pxp: Use the correct define in the set_property_funcs array
  drm/xe/sched: stop re-submitting signalled jobs
  drm/xe: Rework eviction rejection of bound external bos
  drm/xe/vsec: fix CONFIG_INTEL_VSEC dependency
  drm/xe: drop redundant conversion to bool
  drm/xe/hwmon: Move card reactive critical power under channel card
  drm/xe/hwmon: Add support to manage power limits though mailbox
  drm/xe/vm: move xe_svm_init() earlier
  drm/xe/vm: move rebind_work init earlier
  MAINTAINERS: .mailmap: update Rob Clark's email address
  mailmap: Update entry for Akhil P Oommen
  MAINTAINERS: update my email address
  MAINTAINERS: drop myself as maintainer
  drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup
  drm/amd/display: Fix default DC and AC levels
  ...

1 files changed, 21 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 21b57c29bf7d..c74947705d77 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1009,6 +1009,11 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_vcn_inst *vinst)
 
 	jpeg_v1_0_start(adev, 0);
 
+	/* Keeping one read-back to ensure all register writes are done,
+	 * otherwise it may introduce race conditions.
+	 */
+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
 	return 0;
 }
 
@@ -1154,6 +1159,11 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst)
 
 	jpeg_v1_0_start(adev, 1);
 
+	/* Keeping one read-back to ensure all register writes are done,
+	 * otherwise it may introduce race conditions.
+	 */
+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
 	return 0;
 }
 
@@ -1216,6 +1226,12 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_vcn_inst *vinst)
 
 	vcn_v1_0_enable_clock_gating(vinst);
 	vcn_1_0_enable_static_power_gating(vinst);
+
+	/* Keeping one read-back to ensure all register writes are done,
+	 * otherwise it may introduce race conditions.
+	 */
+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
 	return 0;
 }
 
@@ -1250,6 +1266,11 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
 			~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 
+	/* Keeping one read-back to ensure all register writes are done,
+	 * otherwise it may introduce race conditions.
+	 */
+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+
 	return 0;
 }