Merge tag 'perf-core-for-mingo-5.4-20190814' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core

Pull perf/core improvements and fixes from Arnaldo:

Intel PT:

  Adrian Hunter:

  - Add PEBS via Intel PT support, the kernel bits went via PeterZ.

perf record:

  Alexander Shishkin:

  - Add an option to take an AUX snapshot on exit.

  Tan Xiaojun:

  - Support aarch64 random socket_id assignment, just like was fixed for S/390.

tools:

  Andy Shevchenko:

  - Keep list of tools in alphabetical order on 'make -C tools help'.

perf session:

  Arnaldo Carvalho de Melo:

  - Avoid infinite loop when seeing invalid header.size, reported by
    Vince Weaver using a perf.data fuzzer.

Documentation:

  Vince Weaver:

  - Clarify HEADER_SAMPLE_TOPOLOGY format in the perf.data spec.

perf config:

  Arnaldo Carvalho de Melo:

  - Honour $PERF_CONFIG env var to specify alternate .perfconfig.

perf test:

  Arnaldo Carvalho de Melo:

  - Disable ~/.perfconfig to get default output in 'perf trace' tests.

perf top:

  Arnaldo Carvalho de Melo:

  - Set display thread COMM to help with debugging.

  - Collapse and resort evsels in a group, so that we have output
    similar to 'perf report' when using event groups, i.e.

      perf top -e '{cycles,instructions}'

    Will have two columns, and the instructions one will work.

core:

  Igor Lubashev:

  - Detect if libcap development files are available so that we
    can use capabilities to match the checks made by the kernel instead
    of using plain (geteuid() == 0).

Intel:

  Haiyan Song:

  - Add Icelake V1.00 event file.

perf trace:

  Leo Yan:

  - Fix segmentation fault when access syscall info on arm64.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

1 files changed, 40 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 751567f78567..ee1ccdcf2d30 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
 	return 0;
 }
 
+static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
+{
+	int r;
+
+	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+	if (unlikely(r != 0))
+		return r;
+
+	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+			AMDGPU_GEM_DOMAIN_VRAM);
+	if (!r)
+		adev->gfx.rlc.clear_state_gpu_addr =
+			amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+
+	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+
+	return r;
+}
+
+static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
+{
+	int r;
+
+	if (!adev->gfx.rlc.clear_state_obj)
+		return;
+
+	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+	if (likely(r == 0)) {
+		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+	}
+}
+
 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 {
 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -4785,6 +4818,10 @@ static int gfx_v8_0_hw_init(void *handle)
 	gfx_v8_0_init_golden_registers(adev);
 	gfx_v8_0_constants_init(adev);
 
+	r = gfx_v8_0_csb_vram_pin(adev);
+	if (r)
+		return r;
+
 	r = adev->gfx.rlc.funcs->resume(adev);
 	if (r)
 		return r;
@@ -4901,6 +4938,9 @@ static int gfx_v8_0_hw_fini(void *handle)
 	else
 		pr_err("rlc is busy, skip halt rlc\n");
 	amdgpu_gfx_rlc_exit_safe_mode(adev);
+
+	gfx_v8_0_csb_vram_unpin(adev);
+
 	return 0;
 }