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authorTakashi Iwai <tiwai@suse.de>2020-10-12 16:08:57 +0200
committerTakashi Iwai <tiwai@suse.de>2020-10-12 16:08:57 +0200
commitf401b2c9931a70317b6ac0d3e6020adc3a404cc0 (patch)
treeb73efe177884c84bd86f647e2081583d719dde93 /drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
parenta6e7d0a4bdb02a7a3ffe0b44aaa8842b7efdd056 (diff)
parentc890e30b069a2792a5a34e8510a7a437dd6f5b3d (diff)
Merge tag 'asoc-v5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for v5.10 Not a huge amount going on in the core for ASoC this time but quite a lot of driver activity, especially for the Intel platforms: - Replacement of the DSP driver for some older x86 systems with a new one which was written with closer reference to the DSP firmware so should hopefully be more robust and maintainable. - A big batch of static checker and other fixes for the rest of the x86 DSP drivers. - Cleanup of the error unwinding code from Morimoto-san, hopefully making it more robust. - Helpers for parsing auxiluary devices from the device tree from Stephan Gerhold. - New support for AllWinner A64, Cirrus Logic CS4234, Mediatek MT6359 Microchip S/PDIF TX and RX controllers, Realtek RT1015P, and Texas Instruments J721E, TAS2110, TAS2564 and TAS2764
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 0047da06041f..414548064648 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -179,6 +179,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
case CHIP_VEGA20:
case CHIP_ARCTURUS:
case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
/* enable runpm if runpm=1 */
if (amdgpu_runtime_pm > 0)
adev->runpm = true;
@@ -678,8 +679,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
* in the bitfields */
if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
se_num = 0xffffffff;
+ else if (se_num >= AMDGPU_GFX_MAX_SE)
+ return -EINVAL;
if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
sh_num = 0xffffffff;
+ else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
+ return -EINVAL;
if (info->read_mmr_reg.count > 128)
return -EINVAL;