diff options
| author | Jesse Zhang <jesse.zhang@amd.com> | 2025-07-04 15:17:43 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-07-16 16:17:36 -0400 |
| commit | 9ffab039bcb0bbfade0e659552d2fb912347a871 (patch) | |
| tree | e43eb42742e098a2b6a167ffb225116659d18220 /drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | |
| parent | 78d0a27ae0e2e70b22895f4b388cc0ab88e3c6ca (diff) | |
drm/amdgpu: Replace HQD terminology with slots naming
The term "HQD" is CP-specific and doesn't
accurately describe the queue resources for other IP blocks like SDMA,
VCN, or VPE. This change:
1. Renames `num_hqds` to `num_slots` in amdgpu_kms.c to better reflect
the generic nature of the resource counting
2. Updates the UAPI struct member from `userq_num_hqds` to `userq_num_slots`
3. Maintains the same functionality while using more appropriate terminology
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3d4185a1d938..8a76960803c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -399,7 +399,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, uint32_t ib_size_alignment = 0; enum amd_ip_block_type type; unsigned int num_rings = 0; - uint32_t num_hqds = 0; + uint32_t num_slots = 0; unsigned int i, j; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) @@ -415,7 +415,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, if (!adev->gfx.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) - num_hqds += hweight32(adev->mes.gfx_hqd_mask[i]); + num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); } ib_start_alignment = 32; @@ -430,7 +430,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, if (!adev->sdma.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) - num_hqds += hweight32(adev->mes.compute_hqd_mask[i]); + num_slots += hweight32(adev->mes.compute_hqd_mask[i]); } ib_start_alignment = 32; @@ -445,7 +445,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, if (!adev->gfx.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) - num_hqds += hweight32(adev->mes.sdma_hqd_mask[i]); + num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); } ib_start_alignment = 256; @@ -589,7 +589,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, } result->capabilities_flags = 0; result->available_rings = (1 << num_rings) - 1; - result->userq_num_hqds = num_hqds; + result->userq_num_slots = num_slots; result->ib_start_alignment = ib_start_alignment; result->ib_size_alignment = ib_size_alignment; return 0; |