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| author | Victor Lu <victorchengchi.lu@amd.com> | 2024-07-18 18:01:23 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-12-14 20:03:51 +0100 |
| commit | f034130a7e228ec39561cfced43ab8214f0283b0 (patch) | |
| tree | 70e5309a74bed21f3da7a92690646731175f3a2d /drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | |
| parent | dbb662d6dde29141ba2428ea642c774855477517 (diff) | |
drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih
[ Upstream commit 8b22f048331dfd45fdfbf0efdfb1d43deff7518d ]
Port this change to vega20_ih.c:
commit afbf7955ff01 ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts")
Original commit message:
"Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW."
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c')
0 files changed, 0 insertions, 0 deletions