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authorJudith Mendez <jm@ti.com>2025-08-18 14:26:31 -0500
committerViresh Kumar <viresh.kumar@linaro.org>2025-08-22 12:24:13 +0530
commit37f846830b510121c5364ba7bd23e3d77a83ff9b (patch)
tree30b8201461186d73fb9322a89735f95a87c24352 /drivers/cpufreq
parentf8d63d7e60e8912b5ded72319c305765b0a6322f (diff)
cpufreq: ti: Allow all silicon revisions to support OPPs
More silicon revisions are being defined for AM62x, AM62Px, and AM62ax SoCs. These silicon may also support currently establishes OPPs, so remove the revision limitation in ti-cpufreq and thus determine if an OPP applies with speed grade efuse parsing. Signed-off-by: Judith Mendez <jm@ti.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/ti-cpufreq.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index d6bd0d2dcf15..6ee76f5fe9c5 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -311,10 +311,10 @@ static struct ti_cpufreq_soc_data am3517_soc_data = {
};
static const struct soc_device_attribute k3_cpufreq_soc[] = {
- { .family = "AM62X", .revision = "SR1.0" },
- { .family = "AM62AX", .revision = "SR1.0" },
- { .family = "AM62PX", .revision = "SR1.0" },
- { .family = "AM62DX", .revision = "SR1.0" },
+ { .family = "AM62X", },
+ { .family = "AM62AX", },
+ { .family = "AM62PX", },
+ { .family = "AM62DX", },
{ /* sentinel */ }
};