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| author | Imre Deak <imre.deak@intel.com> | 2025-08-23 09:02:13 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-08-28 16:31:08 +0200 |
| commit | 3c778a98bee16b4c7ba364a0101ee3c399a95b85 (patch) | |
| tree | d3143c77aa9a59767b53f97afda0c8331ba28d64 /drivers/cdx/controller/cdx_rpmsg.c | |
| parent | 87dca4c6a672e8f5f7fa967f1b742c5f4ebd80b7 (diff) | |
drm/dp: Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS
[ Upstream commit a40c5d727b8111b5db424a1e43e14a1dcce1e77f ]
Reading DPCD registers has side-effects in general. In particular
accessing registers outside of the link training register range
(0x102-0x106, 0x202-0x207, 0x200c-0x200f, 0x2216) is explicitly
forbidden by the DP v2.1 Standard, see
3.6.5.1 DPTX AUX Transaction Handling Mandates
3.6.7.4 128b/132b DP Link Layer LTTPR Link Training Mandates
Based on my tests, accessing the DPCD_REV register during the link
training of an UHBR TBT DP tunnel sink leads to link training failures.
Solve the above by using the DP_LANE0_1_STATUS (0x202) register for the
DPCD register access quirk.
Cc: <stable@vger.kernel.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250605082850.65136-2-imre.deak@intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/cdx/controller/cdx_rpmsg.c')
0 files changed, 0 insertions, 0 deletions