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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-07-04 13:21:43 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-07-04 13:21:43 +0200 |
| commit | 5d1191ab6cd82b1347eb1b023a3b1eb36ae74ec9 (patch) | |
| tree | 89a3effc70464c52829afed58bcb4b961df048c5 /arch/x86/kernel/cpu/intel.c | |
| parent | 742c87bf27d3b715820da6f8a81d6357adbf18f8 (diff) | |
| parent | 4a7cb7a96aa32e34777b263fbf372543fb85ddea (diff) | |
Merge back earlier cpufreq material for v4.8.
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 6e2ffbebbcdb..c1a89bc026ac 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c) } /* - * P4 Xeon errata 037 workaround. + * P4 Xeon erratum 037 workaround. * Hardware prefetcher may cause stale data to be loaded into the cache. */ if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { if (msr_set_bit(MSR_IA32_MISC_ENABLE, - MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) - > 0) { + MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { pr_info("CPU: C0 stepping P4 Xeon detected.\n"); - pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); + pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); } } |