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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2018-05-17 17:09:18 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-05-22 18:54:06 +0200 |
| commit | 8e1c285a050ca8bcbe30c47f102497e44319f12c (patch) | |
| tree | d526f661daad8d214df3e616c7fadb5c87dae6bf /arch/x86/include/asm/spec-ctrl.h | |
| parent | 72f46c229ac286c0a734888f50a3af274036290f (diff) | |
x86/speculation: Add virtualized speculative store bypass disable support
commit 11fb0683493b2da112cd64c9dada221b52463bf7 upstream
Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.
Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/x86/include/asm/spec-ctrl.h')
0 files changed, 0 insertions, 0 deletions