Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...

1 files changed, 0 insertions, 280 deletions

diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c
deleted file mode 100644
index 22044fc691ef4..0000000000000
--- a/arch/tile/kernel/irq.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-
-#include <linux/module.h>
-#include <linux/seq_file.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/uaccess.h>
-#include <hv/drv_pcie_rc_intf.h>
-#include <arch/spr_def.h>
-#include <asm/traps.h>
-#include <linux/perf_event.h>
-
-/* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
-#define IS_HW_CLEARED 1
-
-/*
- * The set of interrupts we enable for arch_local_irq_enable().
- * This is initialized to have just a single interrupt that the kernel
- * doesn't actually use as a sentinel.  During kernel init,
- * interrupts are added as the kernel gets prepared to support them.
- * NOTE: we could probably initialize them all statically up front.
- */
-DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) =
-  INITIAL_INTERRUPTS_ENABLED;
-EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask);
-
-/* Define per-tile device interrupt statistics state. */
-DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
-EXPORT_PER_CPU_SYMBOL(irq_stat);
-
-/*
- * Define per-tile irq disable mask; the hardware/HV only has a single
- * mask that we use to implement both masking and disabling.
- */
-static DEFINE_PER_CPU(unsigned long, irq_disable_mask)
-	____cacheline_internodealigned_in_smp;
-
-/*
- * Per-tile IRQ nesting depth.  Used to make sure we enable newly
- * enabled IRQs before exiting the outermost interrupt.
- */
-static DEFINE_PER_CPU(int, irq_depth);
-
-#if CHIP_HAS_IPI()
-/* Use SPRs to manipulate device interrupts. */
-#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
-#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
-#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
-#else
-/* Use HV to manipulate device interrupts. */
-#define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
-#define unmask_irqs(irq_mask) hv_enable_intr(irq_mask)
-#define clear_irqs(irq_mask) hv_clear_intr(irq_mask)
-#endif
-
-/*
- * The interrupt handling path, implemented in terms of HV interrupt
- * emulation on TILEPro, and IPI hardware on TILE-Gx.
- * Entered with interrupts disabled.
- */
-void tile_dev_intr(struct pt_regs *regs, int intnum)
-{
-	int depth = __this_cpu_inc_return(irq_depth);
-	unsigned long original_irqs;
-	unsigned long remaining_irqs;
-	struct pt_regs *old_regs;
-
-#if CHIP_HAS_IPI()
-	/*
-	 * Pending interrupts are listed in an SPR.  We might be
-	 * nested, so be sure to only handle irqs that weren't already
-	 * masked by a previous interrupt.  Then, mask out the ones
-	 * we're going to handle.
-	 */
-	unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
-	original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
-	__insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
-#else
-	/*
-	 * Hypervisor performs the equivalent of the Gx code above and
-	 * then puts the pending interrupt mask into a system save reg
-	 * for us to find.
-	 */
-	original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
-#endif
-	remaining_irqs = original_irqs;
-
-	/* Track time spent here in an interrupt context. */
-	old_regs = set_irq_regs(regs);
-	irq_enter();
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-	/* Debugging check for stack overflow: less than 1/8th stack free? */
-	{
-		long sp = stack_pointer - (long) current_thread_info();
-		if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
-			pr_emerg("%s: stack overflow: %ld\n",
-				 __func__, sp - sizeof(struct thread_info));
-			dump_stack();
-		}
-	}
-#endif
-	while (remaining_irqs) {
-		unsigned long irq = __ffs(remaining_irqs);
-		remaining_irqs &= ~(1UL << irq);
-
-		/* Count device irqs; Linux IPIs are counted elsewhere. */
-		if (irq != IRQ_RESCHEDULE)
-			__this_cpu_inc(irq_stat.irq_dev_intr_count);
-
-		generic_handle_irq(irq);
-	}
-
-	/*
-	 * If we weren't nested, turn on all enabled interrupts,
-	 * including any that were reenabled during interrupt
-	 * handling.
-	 */
-	if (depth == 1)
-		unmask_irqs(~__this_cpu_read(irq_disable_mask));
-
-	__this_cpu_dec(irq_depth);
-
-	/*
-	 * Track time spent against the current process again and
-	 * process any softirqs if they are waiting.
-	 */
-	irq_exit();
-	set_irq_regs(old_regs);
-}
-
-
-/*
- * Remove an irq from the disabled mask.  If we're in an interrupt
- * context, defer enabling the HW interrupt until we leave.
- */
-static void tile_irq_chip_enable(struct irq_data *d)
-{
-	get_cpu_var(irq_disable_mask) &= ~(1UL << d->irq);
-	if (__this_cpu_read(irq_depth) == 0)
-		unmask_irqs(1UL << d->irq);
-	put_cpu_var(irq_disable_mask);
-}
-
-/*
- * Add an irq to the disabled mask.  We disable the HW interrupt
- * immediately so that there's no possibility of it firing.  If we're
- * in an interrupt context, the return path is careful to avoid
- * unmasking a newly disabled interrupt.
- */
-static void tile_irq_chip_disable(struct irq_data *d)
-{
-	get_cpu_var(irq_disable_mask) |= (1UL << d->irq);
-	mask_irqs(1UL << d->irq);
-	put_cpu_var(irq_disable_mask);
-}
-
-/* Mask an interrupt. */
-static void tile_irq_chip_mask(struct irq_data *d)
-{
-	mask_irqs(1UL << d->irq);
-}
-
-/* Unmask an interrupt. */
-static void tile_irq_chip_unmask(struct irq_data *d)
-{
-	unmask_irqs(1UL << d->irq);
-}
-
-/*
- * Clear an interrupt before processing it so that any new assertions
- * will trigger another irq.
- */
-static void tile_irq_chip_ack(struct irq_data *d)
-{
-	if ((unsigned long)irq_data_get_irq_chip_data(d) != IS_HW_CLEARED)
-		clear_irqs(1UL << d->irq);
-}
-
-/*
- * For per-cpu interrupts, we need to avoid unmasking any interrupts
- * that we disabled via disable_percpu_irq().
- */
-static void tile_irq_chip_eoi(struct irq_data *d)
-{
-	if (!(__this_cpu_read(irq_disable_mask) & (1UL << d->irq)))
-		unmask_irqs(1UL << d->irq);
-}
-
-static struct irq_chip tile_irq_chip = {
-	.name = "tile_irq_chip",
-	.irq_enable = tile_irq_chip_enable,
-	.irq_disable = tile_irq_chip_disable,
-	.irq_ack = tile_irq_chip_ack,
-	.irq_eoi = tile_irq_chip_eoi,
-	.irq_mask = tile_irq_chip_mask,
-	.irq_unmask = tile_irq_chip_unmask,
-};
-
-void __init init_IRQ(void)
-{
-	ipi_init();
-}
-
-void setup_irq_regs(void)
-{
-	/* Enable interrupt delivery. */
-	unmask_irqs(~0UL);
-#if CHIP_HAS_IPI()
-	arch_local_irq_unmask(INT_IPI_K);
-#endif
-}
-
-void tile_irq_activate(unsigned int irq, int tile_irq_type)
-{
-	/*
-	 * We use handle_level_irq() by default because the pending
-	 * interrupt vector (whether modeled by the HV on
-	 * TILEPro or implemented in hardware on TILE-Gx) has
-	 * level-style semantics for each bit.  An interrupt fires
-	 * whenever a bit is high, not just at edges.
-	 */
-	irq_flow_handler_t handle = handle_level_irq;
-	if (tile_irq_type == TILE_IRQ_PERCPU)
-		handle = handle_percpu_irq;
-	irq_set_chip_and_handler(irq, &tile_irq_chip, handle);
-
-	/*
-	 * Flag interrupts that are hardware-cleared so that ack()
-	 * won't clear them.
-	 */
-	if (tile_irq_type == TILE_IRQ_HW_CLEAR)
-		irq_set_chip_data(irq, (void *)IS_HW_CLEARED);
-}
-EXPORT_SYMBOL(tile_irq_activate);
-
-
-void ack_bad_irq(unsigned int irq)
-{
-	pr_err("unexpected IRQ trap at vector %02x\n", irq);
-}
-
-/*
- * /proc/interrupts printing:
- */
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
-#ifdef CONFIG_PERF_EVENTS
-	int i;
-
-	seq_printf(p, "%*s: ", prec, "PMI");
-
-	for_each_online_cpu(i)
-		seq_printf(p, "%10llu ", per_cpu(perf_irqs, i));
-	seq_puts(p, "  perf_events\n");
-#endif
-	return 0;
-}
-
-#if CHIP_HAS_IPI()
-int arch_setup_hwirq(unsigned int irq, int node)
-{
-	return irq >= NR_IRQS ? -EINVAL : 0;
-}
-
-void arch_teardown_hwirq(unsigned int irq) { }
-#endif