diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2023-09-15 14:09:44 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-10-12 18:43:43 +0530 |
| commit | 662a601aa355c6917ed2bc1c4e316a4c0ee206ed (patch) | |
| tree | 05c2cd1e24724ffebac8170e0ea70bd6308b1ab1 /arch/riscv/include/asm/hwcap.h | |
| parent | a4f5f39849f39f62f5d4e88cbb600f95f927003d (diff) | |
RISC-V: Detect Zicond from ISA string
The RISC-V integer conditional (Zicond) operation extension defines
standard conditional arithmetic and conditional-select/move operations
which are inspired from the XVentanaCondOps extension. In fact, QEMU
RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through
DT or ACPI.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm/hwcap.h')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0f520f7d058a5..6fc51c1b34cf7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,7 @@ #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_ZICOND 44 #define RISCV_ISA_EXT_MAX 64 |