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| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2025-05-06 08:19:57 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2025-06-05 12:21:59 -0700 |
| commit | 847689d2a0c4b4778459c387ec561465e521d963 (patch) | |
| tree | 6ac43733a689227828655f4ffa5e8e9283744b9e /arch/riscv/include/asm/cacheflush.h | |
| parent | 415a8c81da3dab0a585bd4f8d505a11ad5a171a7 (diff) | |
| parent | eb87e56d651d0a72009842bc0d8eeae7b605c97d (diff) | |
Merge patch series "riscv: Add Zicbop & prefetchw support"
Alexandre Ghiti <alexghiti@rivosinc.com> says:
I found this lost series developed by Guo so here is a respin with the
comments on v2 applied.
This patch series adds Zicbop support and then enables the Linux
prefetch features.
* patches from https://lore.kernel.org/r/20250421142441.395849-1-alexghiti@rivosinc.com:
riscv: xchg: Prefetch the destination word for sc.w
riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop
riscv: Add support for Zicbop
riscv: Introduce Zicbop instructions
Link: https://lore.kernel.org/r/20250421142441.395849-1-alexghiti@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Diffstat (limited to 'arch/riscv/include/asm/cacheflush.h')
| -rw-r--r-- | arch/riscv/include/asm/cacheflush.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8de73f91bfa37..effa02c2e682f 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -80,6 +80,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local); extern unsigned int riscv_cbom_block_size; extern unsigned int riscv_cboz_block_size; +extern unsigned int riscv_cbop_block_size; void riscv_init_cbo_blocksizes(void); #ifdef CONFIG_RISCV_DMA_NONCOHERENT |