diff options
| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
| commit | e219aafe50fd546b8686582ddbafd24c3c2eda04 (patch) | |
| tree | a665e08ca8d42f20ac8e5dcc8565d666cffb26bd /arch/mips/kernel/idle.c | |
| parent | ffe12855a5f7f195589130197558e6a5c276caa4 (diff) | |
| parent | 24c96dc79c5e76d3cff7a33f955a4d3244644766 (diff) | |
Merge back earlier 'pm-domains' material for v4.5.
Diffstat (limited to 'arch/mips/kernel/idle.c')
| -rw-r--r-- | arch/mips/kernel/idle.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index ab1478d5a4db1..46794d64c0bfe 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -134,6 +134,16 @@ void __init check_wait(void) return; } + /* + * MIPSr6 specifies that masked interrupts should unblock an executing + * wait instruction, and thus that it is safe for us to use + * r4k_wait_irqoff. Yippee! + */ + if (cpu_has_mips_r6) { + cpu_wait = r4k_wait_irqoff; + return; + } + switch (current_cpu_type()) { case CPU_R3081: case CPU_R3081E: @@ -155,12 +165,12 @@ void __init check_wait(void) case CPU_4KEC: case CPU_4KSC: case CPU_5KC: + case CPU_5KE: case CPU_25KF: case CPU_PR4450: case CPU_BMIPS3300: case CPU_BMIPS4350: case CPU_BMIPS4380: - case CPU_BMIPS5000: case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: @@ -171,7 +181,9 @@ void __init check_wait(void) case CPU_XLP: cpu_wait = r4k_wait; break; - + case CPU_BMIPS5000: + cpu_wait = r4k_wait_irqoff; + break; case CPU_RM7000: cpu_wait = rm7k_wait_irqoff; break; @@ -196,7 +208,6 @@ void __init check_wait(void) case CPU_INTERAPTIV: case CPU_M5150: case CPU_QEMU_GENERIC: - case CPU_I6400: cpu_wait = r4k_wait; if (read_c0_config7() & MIPS_CONF7_WII) cpu_wait = r4k_wait_irqoff; |