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authorIngo Molnar <mingo@kernel.org>2018-04-12 09:42:34 +0200
committerIngo Molnar <mingo@kernel.org>2018-04-12 09:42:34 +0200
commitef389b734691cdc8beb009dd402135dcdcb86a56 (patch)
tree9523a37db93cb7c7874a5f18b4d9a7014898b814 /arch/m32r/include/asm/cachectl.h
parenta774635db5c430cbf21fa5d2f2df3d23aaa8e782 (diff)
parentc76fc98260751e71c884dc1a18a07e427ef033b5 (diff)
Merge branch 'WIP.x86/asm' into x86/urgent, because the topic is ready
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/m32r/include/asm/cachectl.h')
-rw-r--r--arch/m32r/include/asm/cachectl.h27
1 files changed, 0 insertions, 27 deletions
diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h
deleted file mode 100644
index 12f73f6c17590..0000000000000
--- a/arch/m32r/include/asm/cachectl.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * cachectl.h -- defines for M32R cache control system calls
- *
- * Copyright (C) 2003 by Kazuhiro Inaoka
- */
-#ifndef __ASM_M32R_CACHECTL
-#define __ASM_M32R_CACHECTL
-
-/*
- * Options for cacheflush system call
- *
- * cacheflush() is currently fluch_cache_all().
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE 0 /* make pages cacheable */
-#define UNCACHEABLE 1 /* make pages uncacheable */
-
-#endif /* __ASM_M32R_CACHECTL */