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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-03 11:52:33 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-03 11:52:33 +0100 |
| commit | 56f68556d7bbb51dd158c74deb09c783345bfbbd (patch) | |
| tree | 536e6e3c7063b1eee927194dda257602bd3dc66f /arch/blackfin/include/asm/cache.h | |
| parent | fd9470ce3ac6fb54d6026e4b1cdab0936e34805e (diff) | |
| parent | 7c8ad9828e793573877fd60868bb5d2f1e3b64da (diff) | |
Merge unstable branch 'omap-rmk'
Merge branch 'omap-rmk' into omap-all
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
| -rw-r--r-- | arch/blackfin/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h new file mode 100644 index 0000000000000..023d72133b5a1 --- /dev/null +++ b/arch/blackfin/include/asm/cache.h @@ -0,0 +1,29 @@ +/* + * include/asm-blackfin/cache.h + */ +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#endif |