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authorArnd Bergmann <arnd@arndb.de>2012-07-02 22:53:37 +0200
committerArnd Bergmann <arnd@arndb.de>2012-07-02 22:53:37 +0200
commitdf7cb455850351aa2793ffb41f6a2dcaefd83d9b (patch)
tree374f84ee13239586a6754be3cab60e81bfe7ddeb /arch/arm/mach-at91/gpio.c
parent6887a4131da3adaab011613776d865f4bcfb5678 (diff)
parentc4b68520dc0ec96153bc0d87bca5ffba508edfcf (diff)
Merge tag 'at91-for-next-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
Nicolas Ferre <nicolas.ferre@atmel.com> writes: A series about interrupt controller cleanup. AT91 AIC is moving to fasteoi type of handler and sparse IRQ. The Device Tree support is added to take into account priority and external IRQ. In addition to that, the new AIC5 IP is introduced. Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'at91-for-next-cleanup' of git://github.com/at91linux/linux-at91: ARM: at91: add AIC5 support ARM: at91: remove mach/irqs.h ARM: at91: sparse irq support ARM: at91: at91 based machines specify their own irq handler at run time ARM: at91: remove static irq priorities for sam9x5 ARM: at91: add of irq priorities support ARM: at91: aic add dt support for external irqs ARM: at91: aic can use fast eoi handler type ARM: at91: fix at91_aic_write macro ARM: at91: remove two unused headers
Diffstat (limited to 'arch/arm/mach-at91/gpio.c')
-rw-r--r--arch/arm/mach-at91/gpio.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 325837a264c9..be42cf0e74bd 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -26,6 +26,8 @@
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
+#include <asm/mach/irq.h>
+
#include <mach/hardware.h>
#include <mach/at91_pio.h>
@@ -585,15 +587,14 @@ static struct irq_chip gpio_irqchip = {
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_data *idata = irq_desc_get_irq_data(desc);
- struct irq_chip *chip = irq_data_get_irq_chip(idata);
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
void __iomem *pio = at91_gpio->regbase;
unsigned long isr;
int n;
- /* temporarily mask (level sensitive) parent IRQ */
- chip->irq_ack(idata);
+ chained_irq_enter(chip, desc);
for (;;) {
/* Reading ISR acks pending (edge triggered) GPIO interrupts.
* When there none are pending, we're finished unless we need
@@ -614,7 +615,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
}
}
- chip->irq_unmask(idata);
+ chained_irq_exit(chip, desc);
/* now it may re-trigger */
}