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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2015-12-21 03:14:03 +0100
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2015-12-21 03:14:03 +0100
commite219aafe50fd546b8686582ddbafd24c3c2eda04 (patch)
treea665e08ca8d42f20ac8e5dcc8565d666cffb26bd /arch/arm/kernel/devtree.c
parentffe12855a5f7f195589130197558e6a5c276caa4 (diff)
parent24c96dc79c5e76d3cff7a33f955a4d3244644766 (diff)
Merge back earlier 'pm-domains' material for v4.5.
Diffstat (limited to 'arch/arm/kernel/devtree.c')
-rw-r--r--arch/arm/kernel/devtree.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 11c54de9f8cfa..65addcbf5b308 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -101,6 +101,7 @@ void __init arm_dt_init_cpu_maps(void)
if (of_property_read_u32(cpu, "reg", &hwid)) {
pr_debug(" * %s missing reg property\n",
cpu->full_name);
+ of_node_put(cpu);
return;
}
@@ -108,8 +109,10 @@ void __init arm_dt_init_cpu_maps(void)
* 8 MSBs must be set to 0 in the DT since the reg property
* defines the MPIDR[23:0].
*/
- if (hwid & ~MPIDR_HWID_BITMASK)
+ if (hwid & ~MPIDR_HWID_BITMASK) {
+ of_node_put(cpu);
return;
+ }
/*
* Duplicate MPIDRs are a recipe for disaster.
@@ -119,9 +122,11 @@ void __init arm_dt_init_cpu_maps(void)
* to avoid matching valid MPIDR[23:0] values.
*/
for (j = 0; j < cpuidx; j++)
- if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
- "properties in the DT\n"))
+ if (WARN(tmp_map[j] == hwid,
+ "Duplicate /cpu reg properties in the DT\n")) {
+ of_node_put(cpu);
return;
+ }
/*
* Build a stashed array of MPIDR values. Numbering scheme
@@ -143,6 +148,7 @@ void __init arm_dt_init_cpu_maps(void)
"max cores %u, capping them\n",
cpuidx, nr_cpu_ids)) {
cpuidx = nr_cpu_ids;
+ of_node_put(cpu);
break;
}