diff options
| author | Adam Ford <aford173@gmail.com> | 2025-06-20 16:34:45 -0500 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2025-07-11 16:34:31 +0800 |
| commit | f83f69097a302ed2a2775975ddcf12e6a5ac6ec3 (patch) | |
| tree | 34700aa88e3693b3cf8e1364988c5a0e38711875 | |
| parent | 2e87fbee1df502246d7c95988ed078500bad7dd8 (diff) | |
arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed
The reference manual for the i.MX8MM states the clock rate in
MMC mode is 1/2 of the input clock, therefore to properly run
at HS400 rates, the input clock must be 400MHz to operate at
200MHz. Currently the clock is set to 200MHz which is half the
rate it should be, so the throughput is half of what it should be
for HS400 operation.
Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 21bcd82fd092..8287a7f66ed3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -294,6 +294,8 @@ pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; + assigned-clock-rates = <400000000>; bus-width = <8>; non-removable; status = "okay"; |